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MIL-PRF-38534 CERTIFIED
M.S.KENNEDY CORP.
4707 Dey Road Liverpool, N.Y. 13088
600V ISOLATED HALF BRIDGE GATE DRIVER
4900
(315) 701-6751
FEATURES:
Floating Channels up to 600V Up to 8 Amp Peak Source and Sink Current De-Saturation Protection/Shutdown Individual ON, OFF and Soft Shutdown Pins for Each IGBT Gate Undervoltage Lockout Simultaneous Conduction Lockout Contact MSK for MIL-PRF-38534 Qualification Status
DESCRIPTION:
The MSK 4900 is a complete isolated half bridge gate driver hybrid capable of working to 600V channel isolation and 8 amps peak turn-on and turn-off current. Housed in an isolated, convenient bolt-down hermetic package, the MSK 4900 houses the entire isolated DC-DC converter circuitry and opto-isolators for logic signals. The input logic prevents simultaneous conduction by locking out both high side and low side drives in case both inputs are asserted ON at the same time. Each gate drive is capable of sourcing and sinking up to 8 amps peak current. The turn-on and turn-off pins are separate to allow separate gate current control. Upon detection of a de-saturation condition, a FAULT is presented and the transistor is shutdown by a separate controlled shutdown pin. The FAULT will have to be cleared before normal operation will begin again. The MSK 4900 has good thermal conductivity due to an isolated substrate/package design that allows direct heat sinking of the device without insulators.
EQUIVALENT SCHEMATIC
TYPICAL APPLICATIONS
Inverter Bridge Gate Drive Motor Control Gate Drive Bridge
1
PIN-OUT INFORMATION
TBD
PRELIMINARY Rev. 1/07
ABSOLUTE MAXIMUM RATINGS
High Voltage Isolation Logic Input Voltage Vcc Supply Continuous Output Current Peak Ouput Current Thermal Resistance (output drivers - junction to case)

6
ELECTRICAL SPECIFICATIONS
All Ratings: Tc=+25C Unless Otherwise Specified Parameter
Vcc SUPPLY CHARACTERISTICS Vcc Voltage Vcc Current INPUT/OUTPUT LOGIC Positive Trigger Input Voltage Negative Trigger Input Voltage Open Collector Ouput - VOL Open Collector Ouput - IOL OUTPUT CHARACTERISTICS - GATE DRIVE VOH VOL IOH IOL ISD tplh - Propagation Delay Time tphl - Propagation Delay Time tr - Rise Time tf - Fall Time td - De-Sat Delay Time De-Sat Trip Voltage CL=0.33F, 20KHz pulse 14.25 -5.75 8 8 TBD TBD TBD TBD TBD TBD TBD 15.0 -5.0 TBD TBD TBD TBD TBD TBD TBD 15.75 -4.25 TBD TBD TBD TBD TBD TBD TBD 14.25 -5.75 8 8 TBD TBD TBD TBD TBD TBD TBD 15.0 -5.0 TBD TBD TBD TBD TBD TBD TBD 15.75 -4.25 TBD TBD TBD TBD TBD TBD TBD V V A A S S S S S S V IOL=1.5mA 2.0 0.15 0.8 0.4 1.5 2.0 0.15 0.8 0.4 1.5 V V V mA CL=0.33F, 20KHz pulse 14.25 TBD 15.00 TBD 15.75 TBD 14.25 TBD 15.00 TBD 15.75 TBD V mA
Test Conditions
Group A Subgroup
MSK 4900H/E Min. Typ. Max. Min.
MSK 4900 Typ. Max.
NOTES: 1 2 3 4 5 Guaranteed by design but not tested. Typical parameters are representative of actual device performance but are for reference only. Industrial grade and "E" suffix devices shall be tested to subgroups 1 and 4 unless otherwise specified. Military grade devices ("H" Suffix) shall be 100% tested to Subgroups 1, 2, 3 and 4. Subgroups 5 and 6 testing available upon request. Subgroup 1, 4 TA = TC = +25C 2, 5 TA = TC = +125C 3, 6 TA = TC = -55C Continuous operation at or above absolute maximum ratings may adversly effect the device performance and/or life cycle.
6
2
PRELIMINARY
Rev. - 1/07

TBD
-40C to +85C -55C to +125C +150C

600V 5.5V 18V TBD 8A

TST Storage Temperature Range TLD Lead Temperature Range (10 Seconds) TC Case Operating Temperature MSK4900 MSK4900H/E TJ Junction Temperature
-65C to +150C +300C

Units
APPLICATION NOTES MSK 4900 PIN DESCRIPTIONS
VCC - is the bias supply voltage for supplying the input logic and the power supply for the isolated output. This pin should be bypassed to GND with a 4.7F tantalum capacitor and a 0.1F ceramic capacitor as close this pin and GND as possible. X OFF - is the gate drive output pin for turning the gate off. This pin will sink TBD current. A separate gate resistor shall be selected to tailor the turn-off characteristics. This pin will turn off to -5V.
GND - is the Vcc supply return for the input logic and the internal isolated supply. This GND is completely isolated from the output section. No output returns should connect to this GND in order to preserve isolation. All Vcc bias supply bypass connections should be made as close to this pin as possible. An input ground plane is the most preferred layout for assuring good, low impedance ground, shielding of inputs from noise, etc.
DE-SAT SENSE X - is the input connection for sensing desaturation. This pin shall be connected to the collector of the IGBT. This pin is blanked during switching so that it will not false trip.
X VDD - is the pin for the floating gate supply voltage. TBD capacitance shall be connected between this pin and X VSS as close to the pin as possible. Nominally, this voltage will be +15V with respect to the RETURN X pin and the emitter of the IGBT.
HI - is the input logic pin for commanding the high-side gate drive to turn on. This logic input is TTL compatible. This input is exclusive OR'd with LO to protect against simultaneous turn on of both the high-side and low-side gate drive.
X VSS - is the return pin for the floating gate supply voltage. TBD capacitance shall be connected between this pin and X VDD as close to the pins as possible. Nominally, this voltage will be -5V with respect to the RETURN X pin and the emitter.
LO - is the input logic pin for commanding the low-side gate drive to turn on. This logic input is TTL compatible. This input is exclusive OR'd with HI to protect against simultaneous turn on of both the high-side and low-side gate drive.
X FAULT - is an open collector output for indicating either a de-saturation condition or an undervoltage condition for the gate drive. This output will be cleared upon activation of X FAULT CLEAR.
SS X - is the soft shutdown pin for slowly turning the gate off after a de-saturation condition. This pin is a separate gate turn-off path and requires a separate gate resistor for this special turn-off approach. The resistor should be sized to keep di/ dt from being too high after the de-sat condition.
IN
RETURN X - is the pin for the emitter reference. This pin will be at zero volts to +15V to -5V for the gate drive voltage.
X FAULT CLEAR - is a logic input pin for clearing a FAULT condition. This input should not be activated until shutdown of the affected gate is complete. Allow (TBD) Sec after FAULT before activation of this pin.
X ON - is the gate drive output pin for turning the gate on. This pin will source TBD current. A separate gate resistor shall be selected to tailor the turn-on characteristics. This pin will turn on to +15V.
NOTE: X = HI or LO
3
PRELIMINARY
Rev. - 1/07
TYPICAL APPLICATION
TBD
4
PRELIMINARY
Rev. - 1/07
MSK4900 TEST CIRCUIT
TBD
5
PRELIMINARY
Rev. - 1/07
MECHANICAL SPECIFICATIONS
WEIGHT= TBD GRAMS TYPICAL NOTE: ALL DIMENSIONS ARE 0.010 INCHES UNLESS OTHERWISE LABELED. ESD Triangle indicates Pin 1.
ORDERING INFORMATION
MSK4900 H U
LEAD CONFIGURATION S=STRAIGHT, U=BENT UP, D=BENT DOWN SCREENING BLANK=INDUSTRIAL; E=EXTENDED RELIABILITY; H=MIL-PRF-38534 CLASS H GENERAL PART NUMBER
THE ABOVE EXAMPLE IS A MILITARY GRADE HYBRID WITH LEADS BENT UP.
M.S. Kennedy Corp.
4707 Dey Road, Liverpool, New York 13088 Phone (315) 701-6751 FAX (315) 701-6752 www.mskennedy.com
The information contained herein is believed to be accurate at the time of printing. MSK reserves the right to make changes to its products or specifications without notice, however, and assumes no liability for the use of its products. Please visit our website for the most recent revision of this datasheet. Contact MSK for MIL-PRF-38534 qualification status.
6
PRELIMINARY
Rev. - 1/07

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